The present invention is directed to flip-flops, particularly those of the type employed in dynamic synchronous circuits.
One of the basic elements of many digital systems is the D-type flip-flop. The D-type flip-flop is often used as a synchronous device; the value of its output depends on the value that its input had at the occurrence of the most recent clock signal. In some systems, however, it is desired to be able to reset the D-type flip-flop asynchronously, too; i.e., to reset the flip-flop at a time that is independent of the clock signal. Typically, a reset input terminal is provided, and pulsing the terminal resets the flip-flop.
If the flip-flop is a dynamic circuit--i.e., if it must be refreshed periodically--retention of a given state usually depends on capacitances in the circuit that are able to maintain the necessary charge until the next refresh of the circuit. In some circumstances, however, it is desirable for a dynamic circuit to have the additional capability of being reset in a static manner. For instance, if a synchronous circuit is to be initialized so that all of its flip-flops are reset before the clocking operations begin, the capacitances in the flip-flops will not in general be great enough to maintain the reset condition until synchronous operation starts. Accordingly, additional circuitry is required to provide the static-reset feature, i.e., to keep the flip-flops reset indefinitely. But such additional circuitry can slow the flip-flop considerably.
It is accordingly an object of the present invention to afford the static-reset feature with a minimum of additional circuitry and thereby minimize the reduction in speed that the addition of a static-reset feature causes.